Phase-timed energy discharge control system

ABSTRACT

A phase-timed energy discharge control system having particular utility in applications where high energy electrical pulses are required such as ignition and other spark gap systems. Means are provided for simultaneously impressing a varying input signal on a memory-phase time system and a capacitor-diode energy storage system, the outputs of which are connected to an energy discharge system which is connected in turn to a load. An anti-gate control system operates to control the capacitor-diode energy storage system to prevent premature discharge. A key aspect of the memory-phase timer system is its ability to &#39;&#39;&#39;&#39;remember&#39;&#39;&#39;&#39; a reference input signal, and at a selected phase interval actuate the anti-gate circuit to enable the capacitor-diode energy storage system to discharge to the desired load, such as a spark gap system, through the energy discharge system. Where the varying input signal is synchronized or phase-timed to an extrinsic event, the discharge of the high energy pulses can be adjustably synchronized to the desired phase relationship to said extrinsic event.

United States Patent Ferrill, Jr.

[ Apr. 9, 1974 1 PHASE-TIMED ENERGY DISCHARGE CONTROL SYSTEM [75] Inventor: Herbert E. Ferrill, Jr., Orangevale,

Calif.

[731 Assignees: J. C. Simpon, Citrus Heights, Harry J. R. Phillips, Claremont, both of, Calif. part interest to each [22] Filed: Aug. 28, 1972 [2]] Appl. No.: 284,347

52 us. Cl... 315/209 T, sis/209 co, 315/209 so 511 Int. Cl. F02p 1/00 [58] Field of Search... 315/209 CD, 209 M, 209 SC,

315/209 P2, 209 T; 123/148 E, 148 F Primary ExaminerHerman Karl Saalbach Assistant Examiner.lames B. Mullins Attorney, Agent, or Firm-Edward A. Ansel; Ernest L.

Brown [WETAt) FtY P l-lAE TI'TMER SYSTEM 1 M .20 AT/Brie? E065?! [57] ABSTRACT A phase-timed energy discharge control system having particular utility in applications where high energy electrical pulses are required such as ignition and other spark gap systems. Means are provided for simultaneously impressing a varying input signal on a memory-phase time system and a capacitor-diode energy storage system, the outputs of which are connected to an energy discharge system which is connected in turn to a load. An anti-gate control system operates to control the capacitor-diode energy storage system to prevent premature discharge. A key aspect of the memory-phase timer system is its ability to remember" a reference input signal, and at a selected phase interval actuate the anti-gate circuit to enable the capacitor-diode energy storage system to discharge to the desired load, such as a spark gap system. through the energy discharge system. Where the varying input signal is synchronized or phase-timed to an extrinsic event, the discharge of the high energy pulses can be adjustably synchronized to the desired phase relationship to said extrinsic event.

12 Claims, 13 Drawing Figures ENERETSYSTEM l SYSTEM l I Dl T DISCHARGE SYSTEM PIIIEIIIEIIIIII 9 IQI $803451 SHEET 1 F 4 MEMORY PHASE TIMER I ow CAPACITOR L/ VOLTAGE 4 VOLTAGE DIoDE SCR BOOST DISCHARGE NPUT SYSTEM ENERGY SYSTEM SIGNAL SYSTEM /0 20/ i I 8o ANTI IGNITION O 6 SPARK GAP GATE COIL DISCHARGE SYSTEM 40 I I w T30 .Z I MEMORY PHASE TIMER SYSTEM {E E EF Z 1 lVa.T A( E 5055?] 1 I R2 85 I I SYSTEM I I DI W l i l I 5 603- 32 I I DISCHARGE I SYSTEM I I I D5 CI I I .':l I 1 6/- I I l I l a I 76 I PATENIEIJAPR 9mm 3803Q451 sum 2 BF 4 z cHcs T+ 66 #76: 33

Cl E 4=E E ANTI GATE 7 Z CIRCUIT MEMORY 72 75 CIRCUIT ALTERNATE MEMORY CAPACITOR DISCHARGE ANT/ GA TE CIRCUIT I 4 c2+ R4" RI 7 PATENTEBAPR 91974 SHEEI 3 BF 4 TIMING "106 GENERATOR gg figgg MEMoRY GENERATOR loo cIRcuIT PULSE HIGH ENERGY ENERGY GENERATOR VOLTAGE CHARGING DISCHARGE GENERATO; SYSTEM SYSTEM L ANTI- I054 GATE CIRCUIT IGNITION 2 COIL PATENTEBAPR 9 1914 SHEET UF 4 DISCHARGE SYSTEM |f T I I I 2 l 2 l IA/ 1 H v I VOLTAGE POWER |SOURCE PHASE-TIMED ENERGY DISCHARGE CONTROL SYSTEM BACKGROUND OF THE INVENTION 1. Field of the Invention The field of this invention is phase-timed energy discharge control systems, particularly phase-timed energy discharge control systems where high energy electrical pulses are required such as spark discharge systems, and also extends to ignition systems.

2. Description of the Prior Art Previously known time-controlled systems, particularly those utilizing mechanical timing, are subject to numerous objections. Some are voltage-dependent, and when voltage fluctuations appear, the operation becomes erratic and undependable. In others, when utilized in applications such as automotive ignition, mechanical devices such as distributors have been used for conveying electrical current to spark plugs according to firing order. These devices comprise a contactbreaker with condenser, an ignition cam, the actual distributor and an automatic timing control device which determines the optimum ignition timing suited to the operating conditions of the engine. Such devices are subject to mechanical wear, susceptible to dirt and environmental influence, and requires constant and precise adjustment to maintain the system in optimum running condition. They are also relatively expensive to maintain because of the necessity for frequent adjustment or replacementof components and the attendant labor involved.

Recognizing these difficulties, systems have been developed which recognize the advantages to be had by utilization of solid state current conducting devices which avoid the problems attendant upon the use of moving mechanical parts. But when adapted to an application such as a timed ignition, certain other problems are encountered. Heretofore, with some internal combustion engines, the elimination of the distributor required association of a permanent magnet with the flywheel as well as the addition of an additional high voltage primary coil and low voltage trigger coil as a timing means, with attendant expense. Additionally, to adjust the timing of such a solid state system, it was necessary to mechanically shift either the stator plate upon which these coils were mounted, or the flywheel, to achieve synchronization which is a laborious and expensive operation, particularly when'performed at frequent and regular intervals to maintain optimum performance.

SUMMARY OF THE INVENTION It is the principal object of the present invention to provide a phase-timed energy discharge control system affording high reliability, precise control, and wide frequency range whichis simple and inexpensiveLAnother object is to provide such a system for application to ignition systems for combustion engines whether as original equipment'or as a replacement for existing systems which is inexpensive in cost, simple to install, and which has all of the above-mentioned advantages. The above and other objects and advantages are achieved by the combination of a means for receiving and amplifyin'g an input signal, the output of which is connected to both a memory-phase-time system and a capacitordiode energy storage system, the output of both of which are connected to an energy discharge system adapted to be connected to a load. An anti-gate control system operates to control the capacitor-diode energy storage system to prevent premature discharge. A key aspect of the memory-phase timer system is its ability to remember a reference input signal, and at a selected phase interval actuate the anti-gate circuit to enable the capacitor-diode energy storage system to discharge through the energy discharge system to the desired load. Where the varying input signal is synchronized or phase-timed to an extrinsic event, the discharge of the high energy pulses can be adjustably synchronized to the desired phase relationship to said extrinsic event.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of the phase-timed control system of the present invention utilized in conjunction with a spark gap discharge means;

FIG. 2 is an electrical schematic circuit diagram of a preferred embodiment of the system of FIG. 1;

FIG. 3 A is a schematiccircuit diagram of the memory phase timing circuit of the present invention;

FIG. 3 B graphically illustrates the voltage-time relationship with respect to the R-C network during the operation of the circuit of FIG. 3 A;

FIG. 4 A is a schematic circuit diagram of the novel anti-gate circuit of the present invention;

FIG. 4 B is a chart of the voltate-time relationship existing during the operation of the circuit of FIG. 4 A;

FIG. 5 A is a schematic circuit diagram of the memory and capacitordischarge and gate circuits of the present invention, redrawn in a manner which facilitates an understanding of their operation;

FIG. 5 B is a chart showing the voltage-time relationship existing with respect to several key components of the circuit of FIG. 5 A;

FIG. 6 is an electrical schematic circuit diagram of another embodiment of the memory phase timing circuit of the present invention;

FIG. 7 is a block diagram of an embodiment of the present invention adapted for use as a phase-timed control ignition systemfor an -internal combustion automotive engine;

FIG. 8 is an electrical schematic diagram of the embodiment of FIG. 7;

FIG. 9 isa modification of the embodiment of FIG. 2 which has particular utility in a motorcycle ignition system; and

FIG. 10 is an electricalschematic of a further modification especially useful in a motorcycle ignition system.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. I of the drawings, which is a block diagram of the phase-timed control system of the'present invention, there is shown a variable voltage signal source 10. The voltage level of the signal source 10 is raised by the voltage boost system 20 to which it is connected, the boost system output being connected to the memory phase time system 30 as well as the capacitor diode energy charging system 40. The output of the memory phase timer circuit 30 and the capacitor-diode energy charging system 40 are connected to energy' discharge system 60. It is the function of the memory phase time system 30 to store the appropriate reference input signal, compare the reference to the excursions of the signal voltage on a voltage versus time basis, and supply a trigger signal to the energy discharge system 60 at the appropriate phase time interval for discharge. The capacitor-diode energy storage system 40 serves to store a high energy charge until the appropriate time for discharge through the energy discharge system 60 as indicated by receipt of a trigger signal from the memory phase timer 30. The capacitor-diode energy storage system 40 is further protected against premature discharge by an anti-gate system 50. At the proper time, the energy discharge system 60 discharges a high energy pulse through a load 70, which in the embodiments of the figures shown in an ignition coil which transforms the high current output to a high energy discharge voltage, shown here to be connected to a sparking discharge system 80. The spark gap has come to be the favored ignition means in power plants such as the internal combustion engine. The spark gap has also found application as a light source, being useful in photomicrography of living specimens and shadowgraphy photography of high speed phenomena because it is a high intensity light source of extremely short duration.

Referring also now to FIG. 2, a variable voltage input signal source 'is impressed across the input terminals 22, 24 of the voltage boost system which, in the embodiment illustrated, is a transformer 26. The transformer output is connected to both the memory phase timer circuit 30 and the capacitor-diode energy storage system 40. One terminal 28 of the secondary winding of the transformer 26 connects to the memory phase timer 30 by being connected to the memory capacitor 31 and, the memory potentiometer 32 through the memory load dropping resistor 33. A blocking 34 is connected between the opposite side of the memory capacitor 31 and the movable arm 35 of the memory potentiometer 32. Said opposite side of the memory capacitor 31 also is connected to the anti-gate system 50 and high voltage power source 70 through blocking diode 36 in a manner to be later described, while the opposite terminal of the memory potentiometer 32 is connected to the anti-gate system 50 and the discharge system 60 as will be further explained. The first transformer output terminal 28 is also connected to ground through a blocking diode 42 and an energy storage capacitor 61 which, as part of the discharge system 60, stores and supplies the high current on discharge. The output terminal 28 also connects to the high voltage powerv source 70 at the input lead 74 of the ignition coil 72 through said blocking diode 42 and a silicon controlled rectifier (hereinafter sometimes SCR) 62, which is paralleled by a shunt diode 44. The function of the shunt diode 44 is to protect the SCR 62 from high voltage feedback from the coil 72-capacitor 61 circuit. The silicon controlled rectifier 62 comprises an anode 64, cathode 66 and gate electrode 68.

A silicon controlled rectifier is a semiconductor device consisting of four alternate layers of n and p type silicon which functions as a current controlled switch. Two outstanding features are associated with the SCR, namely, the speed of switching and ratio of controlled to controlling currents. Load currents of tens to hundreds of amperes may be turned on in a few microseconds and turned off in about ten times as long a time. Typically, the controlling current is several orders of magnitude less than the controlled current. In operation, a comparatively small anode current flows when the gate current is zero and the anode-to-cathode voltage is held below a critical value known as the forward breakover voltage. A positive pulse of gate current of suitable magnitude triggers the device into a high conduction mode at which time the anode current is determined also entirely by the characteristics of the external circuit in series with the anode-cathode path, providing this current exceeds a small minimum value called the holding current. Once the high conduction mode is achieved, the gate current has no further control over the anode current. To turn off the anode current, the anode-to-cathode voltage must be reduced substantially (so that the anode current falls below the holding current). For turn off in minimum time, it is necessary to reverse the polarity of the anode voltage.

The other terminal 29 of the secondary winding of transformer 26 connects to a diode 52 and gate bleeder resistance 54 in parallel which together connect to the memory potentiometer 32 as previously described. The diode 52 functions to provide direct current from the transformer 26 to the memory circuit 30. The diode 52- resistance 54 pair also connect to the gate electrode 68 of the silicon controlled rectifier 62 as well as the secondary winding of the ignition coil 72 at the input lead 74, through a gate resistance 56. The secondary winding 75 of the ignition coil 72 is connected through its output lead 76 to the spark gap discharge system 80 which may be one or more conventional spark plugs for use in an internal combustion engine, an explosive bridgewire, a current welding application, or a device of the type shown in U.S. Pat. No. 2,979,640 to Edmonson, entitled Spark Gap, issued Apr. 11, l96l, which can be used for light as well as ignition means. Alternatively, the load 70 and spark gap discharge system 80 could be replaced by an arrangement requiring a high current, short time pulse of high intensity.

In operation, an input signal is impressed across the input terminals 22, 24 of the input transformer 26. This signal can come from any number of sources, such as the existing magneto light and battery charging circuit of a vehicle when the present invention is used to control an ignition system. Where a magneto or alternator were used, it would have a regular alternating current output, the voltage waveform of which was in synchronized relation to the position of the pistons in the internal combustion engine which drove the magneto or alternator. v

The output from the secondary winding of the transformer 26 is rectified by the diodes 42, 52 to charge the energy storage capacitor 61. To complete the circuit current flows to ground, through the primary winding of the coil 72 and through the gate load resistance 56, thereby reversing the potential across the SCR gate electrode 68, keeping the SCR 62 in an off condition. This insures that there is no capacitor discharge during the rise time of C and C The memory phase timer circuit 30 will also receive a positive pulse from the secondary winding of transformer 26, the current being rectified by the memory circuit diode 52, the amount of current being determined by the total diode 52-potentiometer 32-load dropping resistor 33 impedance presented to the output terminals 28, 29 of the transfonner 26. The positive pulse across the potentiometer 32 is impressed on the memory capacitor 31 through the blocking diode 34, the voltage value of the charge on the memory capacitor 31 being dependent upon the position of the arm 35 on the resistance element of the memory potentiometer 32. The diode 34 functions to supply a charging path to the memory capacitor 31 and blocks discharge of the capacitor 31 directly into the memory potentiometer and back through the voltage source.

As best shown in FIGS. 3 A and 3 B, the pulses impressed across the input terminals 22, 24 of the transformer 26 will appear as high voltage alternating current at the output terminals 28, 29 of the secondary winding where it will be rectified by the diode 52 so that direct current pulses are impressed across the memory potentiometer 32. With the potentiometer arm 35 set at the approximate center of the resistance element of the potentiometer, the memory capacitor 31 will be charged to approximately one-half of the potential appearing across the potentiometer 32. As shown in FIG. 3 B, the time-memory capacitor 31 charges during the positive voltage time rise period of 90 electrical degrees. The capacitor 31 stores one-half of the peak voltage of the memory potentiometer 32- diode 52 network. This memory capacitor circuit senses only differential voltage and not total voltage value, the differential between the capacitor 31 and the memory potentiometer 32-diode 52 voltage source being zero until the source becomes lower in potential. In other words, since the capacitor 31 is charged to about one-half the value of the voltage across the memory potentiometer 32 when the voltage reaches its peak value, the capacitor 31 will hold its charge although the potential across the memory potentiometer 32 decreases from maximum voltage. However the voltage across the memory potentiometer 32 will equal the charge on the capacitor 31 at about 135 of the cycle, and as the voltage lowers, the capacitor 31 begins to discharge. Thus, what has been described heretofore is an arrangement providing timing in unison with a mechanical magneto motive force which is not sensitive to voltage variations. The memory circuit described remembers a voltage level and compares it-to a charging level which is a phase-timed to a mechanical movement. The circuit is relatively independent of the source voltage level and as a result the phasing sequence will be locked into a stable occurrence, irrespective of the input voltage frequency or level. The timing, that is the point of timing capacitor discharge, can be adjusted to any timing position of the mechanical system by adjustment of the memory potentiometer 32.

When the memory capacitor 31 was charging, the energy storage capacitor 61 was also being charged. As shown in FIGS. 4 A and 4 B, asthe energy storage capacitor 61 begins to charge, the large current flow through the gate resistance 56 causes a large drop across it.'At any particular time the voltage drop across the gate resistance is equal to the difference between the output voltage from the input transformer 26 and the voltage charge of the enegy storage capacitor 61. Since the voltage across the gate resistance 56 is negative at the junction with the gate electrode 68 of the SCR 62, it serves as a reverse bias on the gate electrode 68 and prevents gating except under the following described circumstances.

When the memory capacitor 31 begins to discharge, a differential voltage is created and a current flows from memory capacitor 31 through the gate diode 36, the gate resistor 56, the gate bleeder resistance 54, the

secondary winding of the input transformer 26, the

has been found that the circuit functions equally well i at higher current flows where the timing capacitor 31 is connected to ground through the gate diode 36, the

connection to the SCR cathode electrode 66 being completed through the primary winding of the output coil 72, which is shown as grounded at one end. The current through the gate resistance 56 will provide a current pulse of the proper polarity on the gate electrode 68 sufficient to trigger the SCR 62 into its high conduction mode, thereby providing an extremely low impedance path to ground for the energy storage capacitor 61 through the primary winding of the output coil 72. This causes the capacitor 61 to discharge, the collapsing field in the primary winding causing an extremely high voltage-high energy pulse to appear at the output terminal 76 of the output coil secondary winding for discharge into a sparking plug and distribution system, an exploding bridgewire, a schlieren system light source, a current welding apparatus, or other application where an electrical impulse of this nature which is synchronized with an external event represented by a corresponding signal or clock pulse is required. This sequence is graphically illustrated in FIGS. 5 A and 5 B where it is seen that from time -to time the voltage across the memory potentiometer 32 and the memory capacitor 31 rises. After the voltage across thememory potentiometer 32 drops to-the same as the charge potential of the memory capacitor 31, the voltage across the gate resistor 56 rises at the same slope or rate that the voltage drops across the memory potentiometer 32. When the voltage across the gate resistor 56 rises to the trigger level of the SCR 62, it gates and the energy storage capacitor discharges in the manner previously described.

FIG. 6 is an alternateembodiment of the present invention. The circuitry is substantially identical'to the circuit shown inFlG. 2. In the circuit of FIG. 6 however the memory load resistance 33 of FIG. 2 is omitted and the voltage supply for the memory circuit is obtained from a lower tap 37 of the secondary winding of the input transformer 26.

Referring now to FIG 7, there is shown a block'diagram of an embodiment of the phase-timed concept of the present invention utilized in a pointless automotive type ignition system. A synchronized pulse generating means connects both to a timing generator memory circuit 102 and a high voltage generator 103. The timing generator memory circuit 102 is coupled to the input of a trigger voltage generator 106, while the output of the high voltage generator circuit 103 is connected to an energy charging system 104, the operation of which is controlled by'an anti-gate circuit of the type previously described. The outputs of the trigger voltage generator 106, the energy charging system 104 and the anti-gate circuit 105 all input to the energy discharge system 107, the output of which is connected to the load which, in this instance, consists of an ignition coil 108 and automotive spark plug system, not shown. To operate, a synchronized pulse is generated from the pulse generator 100, such as from a magnetic coil mounted near the automotive distributor cam, the pulse being fed into the timing circuit 102, the high voltage generator 103, and the trigger voltage generator 106. For example, an electromagnet wound on a permanent magnet core can be mounted near the distributor cam. When the cam moves in the vicinity of the electromagnet, the magnetic lines of force through the coil charge and a voltage is induced in the winding, the output of which is a pulse. Thus, the cam lobe in the existing distributor can be used, a new pick-up coil added, and conventional breaker points eliminated.

The timing generator memory circuit 102 stores the pulses for later comparison and also sends appropriate signals to the trigger voltage generator 106. The pulses also serve to actuate the high voltage generator 103 in a manner to be later described, the output of which causes the energy charging system 104 to store a large amount of high voltage energy. The anti-gate circuit 105 prevents the energy charging system 104 from discharging until such time as an appropriate signal is received from the trigger voltage generator 106 at which time it triggers the energy discharge system 107 to discharge through the ignition coil 108 and spark gap ignition system in synchronism with the cam lobe of the pulse generator 100, to cause ignition of fuel in the internal combustion engine.

FIG. 8 is an electrical schematic diagram of the automotive phase-timed ignition system and shows a magnetic coil 110 which is preferably mounted on the automotive distributor using the rotating distributor cam lobes to induce voltage therein, in the manner previously described. One side of the coil 110 is connected to the Q pulse generator amplifier transistor 112 through its base electrode 116, the other end of the 110 being connected to the transistor emitter 114 through a DC. blocking capacitor 111. In this embodiment, each transistor device comprises a semi-conductive body having a base electrode, an emitter electrode, and

a collector electrode in contact therewith. The semiconductive body may consist, for example, of a germanium or silicon crystal. The base electrode is in low resistance contact with the crystal and may, for example, be a large-area electrode. The emitter and collector electrodes are in rectifying contact with the crystal and may consist of point electrodes, line electrodes or even large-area electrodes. For operation as an amplifier, a bias in the forward direction is impressed between emitter and base while a bias voltage in the reverse direction is applied between collector and base. Assuming the crystal is of the PNP junction type, the emitter should be positive with respect to the base while the collector should be negative with respect to the base. If the crystal is of the NPN junction type, the potentials must be reversed. The transistor 112 illustrated in FIG. 8 employs PNP junction type transistors, althoughNPN junction type may be used, providing the polarity of the biasing voltage is reversed.

A biasing voltage is impressed on the bias input electrode 120 which connects to the Q, transistor emitter 114 through the memory potentiometer 122 which is also connected to the input coil 110. The timing generator memory circuit 102 comprises the potentiometer 122 which connects on its bias input side to a memorytiming capacitor 126, the other side of the capacitor 126 being connected to the base electrode 154 of the Q trigger detector amplifier transitor 150 through a diode 124. The latter side of the timing capacitor 126 is also connected to an intermediate position on the memory circuit potentiometer 122 through a D diode 125 and a movable arm 123 thereby functioning as voltage divider and impressing a value across the memory capacitor 126 which is less than the value of the voltage drop across the memory potentiometer 122.

The collector electrode 118 of the pulse generator amplifier transistor 112 connects to the 0 high voltage pulse driver transistor 128 through its base electrode 132. The emitter electrode 130 of this NPN transistor 128 is grounded while the collector electrode 134 couples this pulse drive transistor 128 to the Q high voltage amplifier transistor 136 through the base electrode 140 of the latter. The collector electrode 142 of this PNP transistor 136 is grounded while the emitter electrode 138 connects to the bias input electrode 120 through the primary winding 146 of the T transformer 144.

The trigger voltage generator circuit 106 comprises the combination of the Q trigger detector amplifier transistor 150 and the trigger driver transistor 160. As shown in FIG. 8, the emitter electrode 152 of the trigger detector amplifier transistor 150 is connected to the memory potentiometer 122 and the input coil 110 through the blocking capacitor 111 while the collector electrode 156 connects to the base electrode 164 of the trigger driver transistor 160, the collector electrode 166 of which is connected to the bias input electrode 120 through the collector load resistance 158 and the emitter electrode 162 of which is connected to the gate electrode 176 of the silicon controlled rectifier (SCR) 170 of the energy discharge system 107 in a manner to be later described.

The remainder of the system, the energy charging system 104, the anti-gate circuit 105, the energy discharge system 107 and the load, namely the ignition coil 108 and the spark plug system are substantially identical to the circuitry previously described, as in FIG. 2. Thus the secondary winding 148 of the transformer 144 connects to the storage capacitor 182 through a diode 178, the capacitor being connected to ground. The circuit is completed by the serial connection of the other side of the secondary winding 148 to ground through the SCR gate electrode load resistance 168 and the primary winding 186 of the output coil 184. The anode electrode 172 of the SCR 170 is connected to the ungrounded side of the charging capacitor 182 while the cathode electrode 174 is connected to ground through the primary winding 186 of the output coil 184. A diode shunts the SCR 170 between anode 172 and cathode 174, protecting the SCR from high voltage feedback from the coil l84-capacitor 182 circuit. One side of the secondary winding 188 of the ignition output 184 is grounded while the other is connected to an output terminal 190 which in turn connects to a spark plug system which includes a distribution means for applying the spark discharge to selected combustion chambers in accordance wih the position of the automotive distributor cam.

In operation, a synchronized pulse is generated'by the rotation of the distributor cam lobe in the vicinity of the input coil 110 by disturbance of the magnetic field. The pulse is fed to and amplified by the Q, pulse generator amplifier transistor 112 which utilizes the voltage impressed upon the bias input electrode 120 as the'system power source. The Q, transistor operates as switching device, turning on and off the voltage to the timing generator memory circuit 102 which comprises the memory capacitor 126, memory potentiometer 122, and the first and second blocking diodes 124, 125, respectively. The output signal from the pulse generator amplifier transistor 112 is amplified but in the same wave form as the signal generated by the input coil 1 10, and in addition to being fed to the timing generator memory circuit 102 through the Q transistor emitter electrode 1 14, it is fed to the high voltage generator circuit 103 through the connection of Q collector electrode 1 18 to the base electrode 132 of the Q high voltage pulse driver transistor 12 8, driving Q transistor 128 which in turn drives the high voltage transistor 136 which converts the direct current pulses to high voltage alternating current. The Q, transistor 136 operates in a high switching off and on mode, because of the low to high bias produced by the Q pulse driver transistor 128, and impresses a square waveform on the primary winding 146 of the transformer 144.

The rising and collapsing magnetic field of the primary winding 146 causes the induction of a high voltage alternating current across the secodary winding, which is rectified and serves to charge the storage capacitor 182. Also, because of the current flow from the transformer secondary winding 148 through the gate load resistance 168, sufficient bias is placed on the gate electrode 176 to prevent current flow through the SCR 170 input until occurrence of a triggering pulse on the gate electrode 176. 4

Voltage is applied to the-timinggenerator memory circuit by the pulse generator amplifier transistor 112 in a manner previously described, charging the memory capacitor 126 and a voltage equal to the differential between the voltage impressed across the memory potentiometer 122 and the memory capacitor 126 is applied to the Q trigger detector amplifier transistor 1 50 at its emitter electrode 152. Current flow through the Q transistor 150 creates a heavy bias on the trigger driver transistor O in its conduction direction to switch and create a path from the bias input electrode 120 for the current impressed thereon to ground through Q transistor 160, the gate load resistor 168 of the SCR 170, and the primary winding 186 of the output coil 184. the voltage drop caused by the current flow is impressed on the SCR gate electrode 176 and puts the SCR 170 in the conduction mode, thereby discharging the storage capacitor 182 through the SCR 170 and the primary winding 186 of the output coil 184 where an even higher counter-e.'m.f. is induced in the secondary winding 188 and impressed on the output terminal 190 where it is selectively distributed to the spark plugs in the various combustion chanbers in accordance with the excursions of the distributor cam lobe which together with the input coil 1 is the source of the input pulses which actuate the present system.

FIG. 9 discloses a modification of the embodiment shown in FIG. 2, finding particular application as a motorcycle ignition. The circuitry and operation are identical with that of FIG. 2 and bear similar numerical designations with the difference of the serial placement of a variable inductor 38 between the memory load dropping resistor 33 and the memory potentiometer 32. The inductance of variable inductor 38 is changed as the speed increases, thereby advancing frequency of the trigger pulses at higher revolutions per minute (r.p.m.) of the internal combustion engine.

FIG. 10 illustrates a further modification of the circuitry of FIG. 2 which finds particular utility as a motorcycle ignition system, but is not especially limited thereto. In this embodiment an external signal is fed to a voltage boost system 201 which comprises a transformer 200 having a primary winding 202 and first and second secondary windings 204, 206 respectively. The voltage impressed on the primary winding 202 may be an alternating current phase-synchronized with the firing sequence of each combustion chamber of the internal combustion engine, or, in other applications, a clock pulse or wave form having some other phase relation to an external event or events. The output from the second secondary winding 206 is rectified by the D diode 220 to charge the energy storage capacitor 222 which together comprise the energy system 219. The memory phase timer circuit also receives apulse from the first secondary winding204, the current being rectified by the D memory circuit diode 216, the current across the R, potentiometer 210 being impressed on the C memory capacitor 208 through the D blocking diode 212. The voltage value of the charge on the memory capacitor 208 is dependent upon the position of the arm on the resistance element of the potentiometer 210. The diode 212 functions to supply a charging path to the memory capacitor 208 and blocks discharge of the capacitor 208 directly into the memory potentiometer and back through the voltage source, the secondary winding 204.

The silicon controlled rectifier 224 is kept in a nonconductive state by virtue of the votage across the R gate resistance 218 which is impressed on the SCR gate electrode 230 while the capacitor 208 charges to its predetermined value, thereby keeping the energy storage capacitor 222 from discharging. When the memory capacitor 208 begins to discharge, in a manner as previously described, current flows from the capacitor 208 throughthe D diode 214 and the gate resistor 218, providing a current pulse of the proper polarity on the gate electrode 230 sufficient to trigger the SCR 224 into its high conduction mode, thereby providing for activation of the discharge system 225. The discharge system 225 comprises the SCR 224 and the D shunt diode 232 which serves to protect the SCR 224 from high voltage feedback from the L-C circuit comprised of the transformer 234 of the high voltage power source 231 and the storage capacitor 222. The low impedance path provided by the storage capacitor 222, leading from the capacitor 222, the SCR anode 226, the SCR cathode 228, the primary winding 236 of the transformer 234 of the high voltage power source 231,

to ground and back to the capacitor 222, causes the capacitor 222 to discharge. The collapsing field generated by thecurrent flow through the primary winding 236 causes an extremely high voltage-high energy pulse to appear across the secondary winding 238 for discharge into a sparking plug or other system, the distribution means for the particular application being well known to those skilled in the art. ()ne significantadvantage of the circuitry disclosed in FIG. 10 is that the.iso-. lation provided by utilizing a separate transformer winding 204 for the memory control circuit and a separate winding 206 for the energy system 219 and output pulse production results in attentuation of distortion and improvement in stability of the memory control circuit. I

What is claimed is:

l. A phase-timed energy discharge control system comprising:

an electrical energy storage and discharge means;

a pulse-controlled current flow device operatively connected in the discharge path of said energy storage means, said current flow device adapted to interconnect said energy storage and discharge means with a load;

means for controlling the conduction state of said current flow device;

means for storing a reduced percentage of the peak value of an impressed signal and for actuating said current flow device control means when said signal decreases from its peak to said stored reduced percentage of the peak value of said impressed signal; and

means for impressing a cyclic input signal upon said electrical energy storage and discharge means and said means for storing and actuating, to charge said storage and discharge means and said means for storing an impressed reference signal;

whereby the electrical energy in said storage and discharge means is thereafter discharged to a load through said pulse-controlled current flow device at said selected phase interval after the peak of said impressed input signal.

2. A phase-timed energy discharge control system comprising:

capacitor means for storing and discharging electrical energy;

load terminals;

a silicon controlled rectifier having its anode-cathode circuit operatively connected in the discharge path of said capacitor means to interconnect said capacitor means with said load terminals, and normally being in a non-conductive state;

anti-gating means connected to control the conductive state of said silicon controlled rectifier;

means for storing an impressed signal at a predetermined reference level and causing said anti-gating means to place said silicon controlled rectifier in a conductive state at a selected phase interval after signal storage; and

means for impressing a cyclically varying signal upon said capacitor means and said signal storage means to charge said capacitor means and to establish said reference level in said storage means;

said anti-gating means being connected to be responsive to said varying signals after such signals fall below said reference level to then trigger said silicon controlled rectifier into its conductive state, connecting said capacitor means through said silicon controlled rectifier to said load terminals.

3. A system as claimed in claim 2, and in addition a load connected to said load terminals.

4. A system as claimed in claim 3 wherein said load comprises at least one spark discharge device.

5. A phase-timed energy discharge control system comprising:

a signal amplifying means having an input and an output;

an energy storage capacitor, one side of which is connected to ground;

a first diode connected between said signal amplifying means output and said energy storage capacitor to provide a direct current to charge said capacitor;

an output transformer having a primary and a secondary winding, one side of each being connected to ground;

a silicon controlled rectifier having anode, cathode and gate electrodes, the anode electrode being connected to said energy storage capacitor at its ungrounded side and its cathode being connected to the ground through the primary winding of said transformer;

an oppositely conducting second diode in shunt connection across the anode and cathode electrodes of said silicon controlled rectifier;

a timing capacitor;

means for connecting the output of said signal amplifying means to said timing capacitor;

third diode means coupling said timing capacitor to said silicon controlled rectifier cathode electrode;

a potentiometer having an adjustable intermediate tap connected between said signal amplifying output connection means and timing capacitor on one side, and the gate electrode of said silicon controlled rectifier on the other, the adjustable intermediate tap being connected to said timing capacitor through a fourth blocking diode;

a gate load resistance and a gate bleeder resistance,

said gate resistance being serially connected between the output of said signal amplifying means and ground through the secondary winding of said output transformer and being connected to said silicon controlled rectifier at the junction of said gate resistances;

a fifth diode in shunt connection across said gate bleeder resistance and providing direct current from the output of said signal amplifying means to said potentiometer and said timing capacitor;

the ungrounded side of said output transformer secondary winding being adapted to be connected to a load.

6. A system as claimed in claim 5 and in addition, a variable inductor serially connected between said potentiometer and said signal amplifying output connection means.

7. A phase-timed energy discharge control system comprising:

capacitor means for storing and discharging electrical energy;

load terminals;

a silicon controlled rectifier and an electrical load operatively connected to said load terminals in the discharge path of said capacitor means to interconnect said capacitor means with said load;

means for controlling the conductive state of said silicon controlled rectifier;

electrical storage means for storing an impressed signal at a predetermined reference level less than the peak value of an impressed signal and to trigger said means for controlling and said silicon controlled rectifier into a conductive state when said impressed signal thereafter falls to said reference level; and means for impressing a repetitive electrical input signal upon said capacitor means and said electrical storage means, including a means for synchronizing the generation of each said repetitive electrical input signal with the occurrence of an external event, to cause said capacitor means to discharge through said silicon controlled rectifier at a selected phase interval after the peak of a cycle of said repetitive input signal.

8. A system as described in claim 7 in which said load comprises a spark discharge means, the energization of which is controlled by said means for synchronizing the generation of said repetitive electrical signal.

9. A phase-timed energy discharge control system comprising:

a signal generator amplifier transistor having emitter,

collector and base electrodes;

means for generating a repetitive electrical input signal which is synchronized with the occurrence of an external event, said means being connected between said signal generating transistor base and emitter electrodes;

a bias input electrode;

a timing capacitor;

a potentiometer having an adjustable intermediate tap, said potentiometer being connected to one side to said signal generator amplifier transistor emitter electrode and on the other side joining said timing capacitor in common connection with said bias input electrode;

blocking diode means connecting said timing capacitor with said potentiometer intermediate tap;

a high voltage pulse driver transistor having emitter,

collector and base electrodes; 7

a high voltage amplifier transistor having emitter,

collector and base electrodes;

a first transformer having a first and second winding;

the collector electrode of said signal generator amplifier transistor being directly coupled to the base electrode of said high voltage pulse driver transistor,

the emitter of said pulse driver transistor being at ground potential, and the collector being directly coupled to the base electrode-of said high voltage amplifier transistor,

the collector of said high voltage amplifier transistor being at ground potential and the emitter being connected to said bias input electrode through the first winding of said transformer;

a trigger detector amplifier transistor having emitter,

collector and base electrodes;

a trigger driver transistor having emitter, collector and base electrodes;

a load resistance connecting the collector electrode of said trigger driver transistor with said bias input electrode;

the emitter electrode of said trigger detector amplifier transistor being directly coupled to the emitter electrode of said signal generator amplifier transistor, and the collector electrode of said trigger detector amplifier transistor being directly coupled to the base electrode of said trigger driver transistor;

a current conducting diode in interconnecting said timing capacitor and the base electrode of said trigger detector amplifier transistor;

an energy storage capacitor, one side of which is connected,through a blocking diode to one tenninal of the second winding of said first transformer and the other side connected to ground potential to charge said capacitor;

an output transformer having a primary and a secondary winding, one side of each being connected to ground;

a silicon controlled rectifier having anode, cathode and gate electrodes, the anode electrode being connected to said energy storage capacitor at its ungrounded side and its cathode being connected to ground potential through the primary winding of said output transformer;

gate load resistance interconnecting the gate electrode of said silicon controlled rectifier, the emitter electrode of said trigger driver transistor, and the second terminal of said second winding of said transformer on one side and ground potential through the primary winding of said output transformer on the other.

10. A phase-timed energy discharge control system comprising:

a signal amplifying means having an input and a plurality of outputs;

an energy storage capacitor, one side of which is connected to ground;

a first diode connected between a first of said signal amplifying means outputs and said energy storage capacitor to provide a direct current to charge said capacitor;

an output transformer having a primary and a secondary winding, one side of each being connected to ground;

a silicon controlled rectifier having anode, cathode and gate electrodes, the anode cathode being connected to said energy storage capacitor at the ungrounded side of said capacitor and its cathode being connected to the ground through the primary winding of said output transformer;-

an oppositely conducting diode in shunt connection across the anode and cathode electrodes of said silicon controlled rectifier;

a timing capacitor connected to a second of the outputs of said signal amplifying means;

blocking diode means connecting said timing capacitor to said silicon controlled rectifier cathodeelectrode;

a potentiometer having an adjustable intermediate tap connected between vsaid second of the outputs of said signal amplifying means and said timing capacitor on one side, and the gate electrode of said silicon controlled rectifier on the other, the adjustable intermediate tap being connected between said timing capacitor through a second blocking diode;

a gate resistance and a third diode serially connected between the second of the outputs of said signal amplifying means and ground through th primary winding of said output transformer and being connected to gate electrode said silicon controlled rectifier at the junction of said gate resistance and said third diode; I

the ungrounded side of said output transformer secondary winding being adapted to be connected to a load. I

11. In combination:

a first storage capacitor, connected into a first current path to be charged by current flow in a first direction in said current path to a first polarity voltage;

input voltage means for producing a uni-directional charging current in the first current path;

means for substantially preventing said storage capacitor from charging to a second polarity;

said storage capacitor being connected into a second circuit for discharging of said storage capacitor, said second circuit further comprising the anode to cathode path of a silicon controlled rectifier, said silicon controlled rectifier further having a control electrode for gating the flow of current between the anode and cathode thereof;

means for extracting electrical energy from current flow in said second circuit;

a second memory capacitor, connected into a third circuit to receive a uni-directional charging current flow in synchronism with the charging current flowing into said first capacitor, the peak voltage stored by said second capacitor being controlled to be less than the stored voltage across said first capacitor;

said second capacitor being connected into a fourth circuit, including sensing means to discharge said second capacitor when said input voltage drops substantially to the amplitude of the voltage across said second capacitor; and

means for coupling said control electrode of said silicon controlled rectifier to said fourth circuit to trigger said silicon controlled rectifier when said input voltage drops from its peak to a predetermined percentage of its peak voltage.

12. Apparatus as recited in claim 11 in which said input signal is synchronized with an external event and is cyclic in nature. 

1. A phase-timed energy discharge control system comprising: an electrical energy storage and discharge means; a pulse-controlled current flow device operatively connected in the discharge path of said energy storage means, said current flow device adapted to interconnect said energy storage and discharge means with a load; means for controlling the conduction state of said current flow device; means for storing a reduced percentage of the peak value of an impressed signal and for actuating said current flow device control means when said signal decreases from its peak to said stored reduced percentage of the peak value of said impressed signal; and means for impressing a cyclic input signal upon said electrical energy storage and discharge means and said means for storing and actuating, to charge said storage and discharge means and said means for storing an impressed reference signal; whereby the electrical energy in said storage and discharge means is thereafter discharged to a load through said pulsecontrolled current flow device at said selected phase interval after the peak of said impressed input signal.
 2. A phase-timed energy discharge control system comprising: capacitor means for storing and discharging electrical energy; load terminals; a silicon controlled rectifier having its anode-cathode circuit operatively connected in the discharge path of said capacitor means to interconnect said capacitor means with said load terminals, and normally being in a non-conductive state; anti-gating means connected to control the conductive state of said silicon controlled rectifier; means for storing an impressed signal at a predetermined reference level and causing said anti-gating means to place said silicon controlled rectifier in a conductive state at a selected phase interval after signal storage; and means for impressing a cyclically varying signal upon said capacitor means and said signal storage means to charge said capacitor means and to establish said reference level in said storage means; said anti-gating means being connected to be responsive to said varying signals after such signals fall below said reference level to then trigger said silicon controlled rectifier into its conductive state, connecting said capacitor means through said silicon controlled rectifier to said load terminals.
 3. A system as claimed in claim 2, and in addition a load connected to said load terminals.
 4. A system as claimed in claim 3 wherein said load comprises at least one spark discharge device.
 5. A phase-timed energy discharge control system comprising: a signal amplifying means having an input and an output; an energy storage capacitor, one side of which is connected to ground; a first diode connected between said signal amplifying means output and said energy storage capacitor to provide a direct current to charge said capacitor; an output transformer having a primary and a secondary winding, one side of each being connected to ground; a silicon controlled rectifier having anode, cathode and gate electrodes, the anode electrode being connected to said energy storage capacitor at its ungrounded side and its cathode being connected to the ground through the primary winding of said transformer; an oppositely conducting second diode in shunt connection across the anode and cathode electrodes of said silicon controlled rectifier; a timing capacitor; means for connecting the output of said signal amplifying means to said timing capacitor; third diode means coupling said timing capacitor to said silicon controlled rectifier cathode electrode; a potentiometer having an adjustable intermediate tap connected between said signal amplifying output connection means and timing capacitor on one side, and the gate electrode of said silicon controlled rectifier on the other, the adjustable intermediate tap being connected to said timing capacitor through a fourth blocking diode; a gate load resistance and a gate bleeder resistance, said gate resistance being serially connected between the output of said signal amplifying means and ground through the secondary winding of said output transformer and being connected to said silicon controlled rectifier at the junction of said gate resistances; a fifth diode in shunt connection across said gate bleeder resistance and providing direct current from the output of said signal amplifying means to said potentiometer and said timing capacitor; the ungrounded side of said output transformer secondary winding being adapted to be connected to a load.
 6. A system as claimed in claim 5 and in addition, a variable inductor serially connected between said potentiometer and said signal amplifying output connection means.
 7. A phase-timed energy discharge control system comprising: capacitor means for storing and discharging electrical energy; load terminals; a silicon controlled rectifier and an electrical load operatively connected to said load terminals in the discharge path of said capacitor means to interconnect said capacitor means with said load; means for controlling the conductive state of said silicon controlled rectifier; electrical storage means for storing an impressed signal at a predetermined reference level less than the peak value of an impressed signal and to trigger said means for controlling and said silicon controlled rectifier into a conductive state when said impressed signal thereafter falls to said reference level; and means for impressing a repetitive electrical input signal upon said capacitor means and said electrical storage means, including a means for synchronizing the generation of each said repetitive electrical input signal with the occurrence of an external event, to cause said capacitor means to discharge through said silicon controlled rectifier at a selected phase interval after the peak of a cycle of said repetitive input signal.
 8. A system as described in claim 7 in which said load comprises a spark discharge means, the energization of which is controlled by said means for synchronizing the generation of said repetitive electrical signal.
 9. A phase-timed energy discharge control system comprising: a signal generator amplifier transistor having emitter, collector and base electrodes; means for generating a repetitive electrical input signal which is synchronized with the occurrence of an external event, said means being connected between said signal generating transistor base and emitter electrodes; a bias input electrode; a timing capacitor; a potentiometer having an adjustable intermediate tap, said potentiometer being connected to one side to said signal generator amplifier transistor emitter electrode and on the other side joining said timing capacitor in common connection with said bias input electrode; blocking diode means connecting said timing capacitor with said potentiometer intermediate tap; a high voltage pulse driver transistor having emitter, collector and base electrodes; a high voltage amplifier transistor having emitter, collector and base electrodes; a first transformer having a first and second winding; the collector electrode of said signal generator amplifier transistor being directly coupled to the base electrode of said high voltage pulse driver transistor, the emitter of said pulse driver transistor being at ground potential, and the collector being directly coupled to the base electrode of said high voltage amplifier transistor, the collector of said high voltage Amplifier transistor being at ground potential and the emitter being connected to said bias input electrode through the first winding of said transformer; a trigger detector amplifier transistor having emitter, collector and base electrodes; a trigger driver transistor having emitter, collector and base electrodes; a load resistance connecting the collector electrode of said trigger driver transistor with said bias input electrode; the emitter electrode of said trigger detector amplifier transistor being directly coupled to the emitter electrode of said signal generator amplifier transistor, and the collector electrode of said trigger detector amplifier transistor being directly coupled to the base electrode of said trigger driver transistor; a current conducting diode in interconnecting said timing capacitor and the base electrode of said trigger detector amplifier transistor; an energy storage capacitor, one side of which is connected, through a blocking diode to one terminal of the second winding of said first transformer and the other side connected to ground potential to charge said capacitor; an output transformer having a primary and a secondary winding, one side of each being connected to ground; a silicon controlled rectifier having anode, cathode and gate electrodes, the anode electrode being connected to said energy storage capacitor at its ungrounded side and its cathode being connected to ground potential through the primary winding of said output transformer; a gate load resistance interconnecting the gate electrode of said silicon controlled rectifier, the emitter electrode of said trigger driver transistor, and the second terminal of said second winding of said transformer on one side and ground potential through the primary winding of said output transformer on the other.
 10. A phase-timed energy discharge control system comprising: a signal amplifying means having an input and a plurality of outputs; an energy storage capacitor, one side of which is connected to ground; a first diode connected between a first of said signal amplifying means outputs and said energy storage capacitor to provide a direct current to charge said capacitor; an output transformer having a primary and a secondary winding, one side of each being connected to ground; a silicon controlled rectifier having anode, cathode and gate electrodes, the anode cathode being connected to said energy storage capacitor at the ungrounded side of said capacitor and its cathode being connected to the ground through the primary winding of said output transformer; an oppositely conducting diode in shunt connection across the anode and cathode electrodes of said silicon controlled rectifier; a timing capacitor connected to a second of the outputs of said signal amplifying means; blocking diode means connecting said timing capacitor to said silicon controlled rectifier cathode electrode; a potentiometer having an adjustable intermediate tap connected between said second of the outputs of said signal amplifying means and said timing capacitor on one side, and the gate electrode of said silicon controlled rectifier on the other, the adjustable intermediate tap being connected between said timing capacitor through a second blocking diode; a gate resistance and a third diode serially connected between the second of the outputs of said signal amplifying means and ground through th primary winding of said output transformer and being connected to gate electrode said silicon controlled rectifier at the junction of said gate resistance and said third diode; the ungrounded side of said output transformer secondary winding being adapted to be connected to a load.
 11. In combination: a first storage capacitor, connected into a first current path to be charged by current flow in a first direction in said current path to a first polarity voltage; input voltage means for producing a uni-directional charging current in the first current path; means for substantially preventing said storage capacitor from charging to a second polarity; said storage capacitor being connected into a second circuit for discharging of said storage capacitor, said second circuit further comprising the anode to cathode path of a silicon controlled rectifier, said silicon controlled rectifier further having a control electrode for gating the flow of current between the anode and cathode thereof; means for extracting electrical energy from current flow in said second circuit; a second memory capacitor, connected into a third circuit to receive a uni-directional charging current flow in synchronism with the charging current flowing into said first capacitor, the peak voltage stored by said second capacitor being controlled to be less than the stored voltage across said first capacitor; said second capacitor being connected into a fourth circuit, including sensing means to discharge said second capacitor when said input voltage drops substantially to the amplitude of the voltage across said second capacitor; and means for coupling said control electrode of said silicon controlled rectifier to said fourth circuit to trigger said silicon controlled rectifier when said input voltage drops from its peak to a predetermined percentage of its peak voltage.
 12. Apparatus as recited in claim 11 in which said input signal is synchronized with an external event and is cyclic in nature. 